C8051F970-A-GM Datasheet, PDF (283/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
26.4. Port I/O Modes of Operation
Port pins are configured by firmware as digital or analog I/O using the PnMDIN registers. On reset, all port I/O cells
default to a high impedance state with weak pull-ups enabled. Until the crossbar is enabled, both the high and low
port I/O drive circuits are explicitly disabled on all crossbar pins. Port pins configured as digital I/O may still be used
by analog peripherals; however, this practice is not recommended and may result in measurement errors.
26.4.1. Configuring Port Pins For Analog Modes
Any pins to be used for analog functions should be configured for analog mode. When a pin is configured for
analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins configured for analog functions
will always read back a value of ‘0’ in the corresponding Pn Port Latch register. To configure a pin as analog, the
following steps should be taken:
1. Clear the bit associated with the pin in the PnMDIN register to ‘0’. This selects analog mode for the pin.
2. Set the bit associated with the pin in the Pn register to ‘1’.
3. Skip the bit associated with the pin in the PnSKIP register to ensure the crossbar does not attempt to
assign a function to the pin.
26.4.2. Configuring Port Pins For Digital Modes
Any pins to be used by digital peripherals or as GPIO should be configured as digital I/O (PnMDIN.n = ‘1’). For
digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = ‘1’) drive the port pad to the supply rails based on the output logic value of the
port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to the low-
side rail when the output logic value is ‘0’ and become high impedance inputs (both high low drivers turned off)
when the output logic value is ‘1’.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the high-
side rail to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven
low to minimize power consumption, and they may be globally disabled by setting WEAKPUD to ‘1’. The user
should ensure that digital I/O are always internally or externally pulled or driven to a valid logic state to minimize
power consumption. Port pins configured for digital I/O always read back the logic state of the port pad, regardless
of the output logic value of the port pin.
To configure a pin as digital input:
1. Set the bit associated with the pin in the PnMDIN register to ‘1’. This selects digital mode for the pin.
2. Clear the bit associated with the pin in the PnMDOUT register to ‘0’. This configures the pin as open-drain.
3. Set the bit associated with the pin in the Pn register to ‘1’. This tells the output driver to “drive” logic high.
Because the pin is configured as open-drain, the high-side driver is not active, and the pin may be used as
an input.
Open-drain outputs are configured exactly as digital inputs. However, the pin may be driven low by an assigned
peripheral, or by writing ‘0’ to the associated bit in the Pn register if the signal is a GPIO.
To configure a pin as a digital, push-pull output:
1. Set the bit associated with the pin in the PnMDIN register to ‘1’. This selects digital mode for the pin.
2. Set the bit associated with the pin in the PnMDOUT register to ‘1’. This configures the pin as push-pull.
If a digital pin is to be used as a general-purpose I/O, or with a digital function that is not part of the crossbar, the bit
associated with the pin in the PnSKIP register can be set to ‘1’ to ensure the crossbar does not attempt to assign a
function to the pin.
26.4.3. Port Drive Strength
Port drive strength can be controlled on a pin-by-pin basis using the PnDRV registers. Each pin has a bit in the
associated PnDRV register to select the high or low drive strength setting for the pin. By default, all pins are
configured for low drive strength.
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