C8051F970-A-GM Datasheet, PDF (26/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
2.1.5. Low Power Active Mode
Running in normal active mode can waste a significant amount of amount of power by clocking unused peripherals.
Low power active mode in C8051F97x devices allows control of clocking activity in the clock tree, which enables
firmware to shut off clocking to unused peripherals and save power. The CPU and all the analog and digital
peripherals remain active except those whose clocks are turned off by firmware. The CPU will not be able to
access SFR of peripherals on inactive branches of the clock tree.
Low power active mode is terminated when the CLKMODE register is programmed to 0x00 or a reset occurs.
Systems that use all the peripherals and always stay in the active mode may not find improvement in power
consumption in the low power active mode due overhead logic required for this implementation.
2.1.6. Low Power Idle Mode
In this mode of operation, the CPU is halted and clocks supplied to unused peripherals can be shut down to save
power. All internal registers and memory maintain their original data. All the analog and digital peripherals remain
active except those whose clocks are turned off by user. Modules that are capable of requesting for clocks can do
so at any time.
Low power idle mode is terminated when an enabled interrupt is asserted or a reset occurs, but the interrupt only
causes the device to switch from low power idle mode to low power active mode. To return to normal active mode,
the CLKMODE register should be reset to 0x00. The pending interrupt will be serviced and the next instruction to
be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the
Idle Mode Select bit. If low power idle mode is terminated by an internal or external reset, the CIP-51 performs a
normal sequence and begins program execution at address 0x0000.
2.2. I/O
2.2.1. General Features
The C8051F97x ports have the following features:
Push-pull or open-drain output modes and analog or digital modes.
Port Match allows the device to recognize a change on a port pin value and wake from idle mode or
generate an interrupt.
Internal pull-up resistors can be globally enabled or disabled.
Two external interrupts provide unique interrupt vectors for monitoring time-critical events.
2.2.2. Crossbar
The C8051F97x devices have a digital peripheral crossbar with the following features:
Flexible peripheral assignment to port pins.
Pins can be individually skipped to move peripherals as needed for design or layout considerations.
The crossbar has a fixed priority for each I/O function and assigns these functions to the port pins. When a digital
resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned,
the crossbar skips that pin when assigning the next selected resource. Additionally, the crossbar will skip port pins
whose associated bits in the PnSKIP registers are set. This provides some flexibility when designing a system: pins
involved with sensitive analog measurements can be moved away from digital I/O and peripherals can be moved
around the chip as needed to ease layout constraints.
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