C8051F970-A-GM Datasheet, PDF (383/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
31.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth
data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB8, which is assigned
by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used
in multiprocessor communications. On receive, the ninth data bit goes into RB8 and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI Transmit Interrupt
Flag is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time
after the REN Receive Enable bit is set to 1. After the stop bit is received, the data byte will be loaded into the
SBUF0 receive register if the following conditions are met: (1) RI must be logic 0, and (2) if MCE is logic 1, the 9th
bit must be logic 1 (when MCE is logic 0, the state of the ninth data bit is unimportant). If these conditions are met,
the eight bits of data are stored in SBUF0, the ninth bit is stored in RB8, and the RI flag is set to 1. If the above
conditions are not met, SBUF0 and RB8 will not be loaded and the RI flag will not be set to 1. A UART0 interrupt
will occur if enabled when either TI or RI is set to 1.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
BIT TIMES
BIT SAMPLING
Figure 31.4. 9-Bit UART Timing Diagram
D8
STOP
BIT
384
Rev 1.0