C8051F970-A-GM Datasheet, PDF (340/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 28.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
SPI0CKR
Type
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xA2
Table 28.4. SPI0CKR Register Bit Descriptions
Bit
Name
Function
7:0
SPI0CKR SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is config-
ured for master mode operation. The SCK clock frequency is a divided version of the
system clock, and is given in the following equation, where SYSCLK is the system clock
frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register.
f_SCK = _2----------_--S-S---PY---I-S-0---CC----LK----KR------+-----1---_
for 0 <= SPI0CKR <= 255
Rev 1.0
341