C8051F970-A-GM Datasheet, PDF (54/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
8. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two
separate memory spaces: program memory and data memory. Program and data memory share the same address
space but are accessed via different instruction types. The memory organization of the C8051F97x device family is
shown in Figure 8.1.
PROGRAM/DATA MEMORY
(FLASH)
0x7FFF
0x7FFE
Lock Byte
32 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Registers
(Direct Addressing Only)
(Direct and Indirect Addressing)
32 Bit-Addressable Bytes
32 General Purpose Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0xFFFF
EXTERNAL DATA ADDRESS SPACE
Same 8192 bytes as 0x0000 to 0x1FFF,
wrapped on 8192-byte boundaries
0x0000
0x2000
0x1FFF
0x0000
XRAM - 8192 Bytes
(accessible using MOVX instruction)
Figure 8.1. C8051F97x Memory Map (32 kB Flash Version Shown)
54
Rev 1.0