C8051F970-A-GM Datasheet, PDF (205/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
22.5. MCU Mode Operation
MCU mode operation for the MAC is enabled when there is no DMA channel enabled for transferring data to or
from any MAC0 register. When MCU mode operation is active, the MAC inputs and results are transferred to or
from XRAM via software access to the SFRs. During MCU mode operation, a MAC operation is triggered by
software writing 1 to the BUSY bit in the MAC0STA register. When the MAC operation has completed, hardware
clears the BUSY bit to 0. The typical sequence of MCU mode operations is as follows:
1. Firmware disables all MAC-specific DMA channels.
2. Firmware initializes the control registers (MAC0CF0, MAC0CF1, MAC0CF2, MAC0ITER) appropriately.
3. Firmware writes all the operand values:
Update MAC0A, MAC0B
Setup accumulator either by clearing it (via setting the CLRACC bit) or writing directly to MAC0ACC0-3 and
MAC0OVR
4. Firmware writes 1 to the BUSY bit.
5. MAC0 completes the MAC operation in 1 SYSCLK cycle, clears BUSY bit to 0, and sets both the MACINT
and ACCRDY bits to 1.
22.6. DMA Mode Operation
DMA mode operation is a powerful mode that can be used process large array of data using the MAC0 module.
Alternatively, it can be used to implement digital filters efficiently. DMA mode operation for the MAC0 is enabled
when there is at least one DMA channel enabled for transferring data to or from any MAC0 register.
During DMA mode operation, the BUSY bit must be set to 1 to generate DMA requests. The complete flowchart of
DMA mode operation is given in Figure 22.4.
206
Rev 1.0