C8051F970-A-GM Datasheet, PDF (118/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 17.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
7
6
5
4
3
2
1
0
Name
Reserved
ADTK
Type
R
RW
Reset
0
0
0
1
1
1
1
0
SFR Page = ALL; SFR Address: 0xBC
Table 17.6. ADC0TK Register Bit Descriptions
Bit
Name
Function
7:6
Reserved Must write reset value.
5:0
ADTK Burst Mode Tracking Time.
This field sets the time delay between consecutive conversions performed in Burst
Mode. When ADTM is set, an additional 3 SARCLKs are added to this time.
T_BMTK
=
6---4-----–----A-----D----T----K---
F_HFOSC
The Burst Mode track delay is not inserted prior to the first conversion. The required
tracking time for the first conversion should be defined with the ADPWR field.
118
Rev 1.0