C8051F970-A-GM Datasheet, PDF (368/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30.3.5. DMA and CPU Mode Operations
The I2CSLAVE0 peripheral can operate in either CPU or DMA mode. In CPU mode, all data transfers occur
through software reading from the I2C0DIN register or writing to the I2C0DOUT register. By default, the
I2CSLAVE0 peripheral operates in CPU mode for all I²C Read and Write requests.
In DMA mode, all data transfers are executed by the DMA peripheral automatically without any CPU intervention.
However, I2C0INT must still be cleared by firmware after a START+Slave address has been received. When a
DMA channel has been selected and enabled for data transfer from I2C0DIN to XRAM, the I2CSLAVE0 peripheral
operates in DMA mode for all I²C Write requests. When a DMA channel has been selected and enabled for data
transfer from XRAM to I2C0DOUT, the I2CSLAVE0 peripheral operates in DMA mode for all I²C Read requests.
30.4. Using the I2CSLAVE0 Module
I2CSLAVE0 operates only in Slave mode. The interface provides timing and shifting control for serial transfers;
higher level protocol is determined by user software. The I²C interface provides the following application-
independent features:
Byte-wise serial data transfers
SDA data synchronization
Timeout recognition, as defined by the I2C0CNTL configuration register
START/STOP detection
Interrupt generation
Status information
Interfacing to the DMA to automate data transfers
High-speed I²C mode detection
Automatic wakeup from Sleep mode when matching slave address is received
Hardware recognition of slave address and automatic acknowledgment of address/data
An I2CSLAVE0 interrupt is generated when the RD, WR or STOP bit is set in the I2C0STAT SFR. It is also
generated when the ACTIVE bit goes low to indicate the end of an I²C bus transfer. Refer to the I2C0STAT SFR
definition for complete details on the conditions for the setting and clearing of these bits.
30.4.1. I2C0CNTL Control Register
The I2C0CNTL register is used to control the I2CSLAVE0 interface (see SFR Definition 26.5). The two bits,
I2C0SEL and I2C0EN, are used to enable and disable the I2CSLAVE0 interface and associated pins. The
I2CSLAVE0 peripheral must be enabled in the following sequence:
1. Set I2C0SEL bit in the I2C0CNTL SFR.
2. Set I2C0EN bit in the I2C0CNTL SFR.
This correct sequence of enabling the I2CSLAVE0 ensures the peripheral processes the initial data transfers
correctly.
TOUTEN is used to enable the SCL Low Timeout detection. Refer to section SCL Low Timeout for more details.
PRELOADDIS is used to control whether the data byte must be preloaded before the first SCL clock of an I²C
Read transaction. It should always be set to 1.
BUSY bit controls the automatic hardware acknowledgment of I²C slave address match or I²C Write transactions.
When cleared to 0, automatic hardware acknowledgment is enabled.
30.4.2. I2C0STAT Status Register
The I2C0STAT register is used to provide status information (see SFR Definition 26.4). The HSMODE bit is used to
indicate whether the I2C bus is operating in High-Speed mode as defined in the I2C Specification. This bit is set
after the I2C bus is detected to be operating in HS-mode (refer to section HS-mode for details on how the I2C bus
switch modes). When the I2C bus switches back to F/S-mode operation, the HSMODE bit is cleared.
The setting and clearing of the status bits are described in detail in section I2C Transfer Modes and the SFR
Definition 26.4.
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