C8051F970-A-GM Datasheet, PDF (301/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.17. P2MASK: Port 2 Mask
Bit
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0x84
Table 26.20. P2MASK Register Bit Descriptions
Bit
Name
Function
7
B7
Port 2 Bit 7 Mask Value.
0: P2.7 pin logic value is ignored and will not cause a port mismatch event.
1: P2.7 pin logic value is compared to P2MAT.7.
6
B6
Port 2 Bit 6 Mask Value.
0: P2.6 pin logic value is ignored and will not cause a port mismatch event.
1: P2.6 pin logic value is compared to P2MAT.6.
5
B5
Port 2 Bit 5 Mask Value.
0: P2.5 pin logic value is ignored and will not cause a port mismatch event.
1: P2.5 pin logic value is compared to P2MAT.5.
4
B4
Port 2 Bit 4 Mask Value.
0: P2.4 pin logic value is ignored and will not cause a port mismatch event.
1: P2.4 pin logic value is compared to P2MAT.4.
3
B3
Port 2 Bit 3 Mask Value.
0: P2.3 pin logic value is ignored and will not cause a port mismatch event.
1: P2.3 pin logic value is compared to P2MAT.3.
2
B2
Port 2 Bit 2 Mask Value.
0: P2.2 pin logic value is ignored and will not cause a port mismatch event.
1: P2.2 pin logic value is compared to P2MAT.2.
1
B1
Port 2 Bit 1 Mask Value.
0: P2.1 pin logic value is ignored and will not cause a port mismatch event.
1: P2.1 pin logic value is compared to P2MAT.1.
0
B0
Port 2 Bit 0 Mask Value.
0: P2.0 pin logic value is ignored and will not cause a port mismatch event.
1: P2.0 pin logic value is compared to P2MAT.0.
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Rev 1.0