C8051F970-A-GM Datasheet, PDF (198/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 21.9. DMA0NAOH: Memory Address Offset High
Bit
7
6
5
4
3
2
1
0
Name
Reserved
NAOH
Type
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xCC
Bit
Name
Function
7:2
Reserved Must write reset value.
1:0
NAOH Memory Address Offset High.
This field is the high byte of the channel offset address. The base address added to the
offset address creates the current channel XRAM address. The address offset auto-
increments by one after one byte is transferred. When configuring a channel for a DMA
transfer, the address offset should be reset to 0.
Note: This register is a DMA channel indirect register. Select the desired channel first using the DMA0SEL register.
Rev 1.0
199