C8051F970-A-GM Datasheet, PDF (432/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Offset = 256  PCA0CPL2 + 256 – PCA0L
Equation 33.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and PCA0H.
Software may force a WDT reset by writing a 1 to the CCF2 flag (PCA0CN.2) while the WDT is enabled.
33.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1. Disable the WDT by writing a 0 to the WDTE bit.
2. Select the desired PCA clock source (with the CPS2–CPS0 bits).
3. Load PCA0CPL2 with the desired WDT update offset value.
4. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle mode).
5. Enable the WDT by setting the WDTE bit to 1.
6. Reset the WDT timer by writing to PCA0CPH2.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog timer is
enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the WDT cannot be
disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12,
PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 33.5, this results in a WDT timeout
interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 33.3 lists some example timeout intervals for
typical system clocks.
Table 33.3. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
PCA0CPL2
Timeout Interval (ms)
24,500,000
255
32.1
24,500,000
128
16.2
24,500,000
32
3,062,500²
255
3,062,500²
128
3,062,500²
32
4.1
257
129.5
33.1
32,000
255
24576
32,000
128
12384
32,000
32
3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of
0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Rev 1.0
433