C8051F970-A-GM Datasheet, PDF (367/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the
master cannot force the SCL line high to correct the error condition. To solve this problem, the I2CSLAVE0
peripheral supports a timeout feature to allow the firmware to detect and handle this condition.
This feature is enabled when the TOUTEN bit in I2C0CNTL is set, and Timer 3 is configured to run in 16-bit auto-
reload mode (T3SPLIT set to 0 in TMR3CN). When this feature is enabled, Timer 3 is forced to reload when SCL is
high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after a system-
defined time (and TOUTEN bit set), the Timer 3 interrupt service routine can be used to detect and handle this error
condition.
30.3.4. HS-mode
The I²C Specification supports High-speed mode (HS-mode) transfer which allows devices to transfer data at rates
of up to 3.4 Mbps and yet remain fully downward compatible with slower speed devices. This allows HS-mode
devices to operate in a mixed-speed bus system. Refer to the I²C Specification for details on the electrical and
timing requirements for HS-mode operation. The I2CSLAVE0 peripheral is compatible with the I²C HS-mode
operation without any software intervention other than requiring that firmware enable the I2CSLAVE0 peripheral.
By default, the I²C bus operates at speeds of up to Fast-mode (F/S mode) only, where the maximum transfer rate
is 400 kbps. The I²C bus switches to from F/S mode to HS-mode only after the following sequence of bits appear
on the I²C bus:
1. START bit (S)
2. 8-bit master code (0000 1XXX)
3. NACK bit (N)
The HS-mode master codes are reserved 8-bit codes which are not used for slave addressing or other purposes.
An HS-mode compatible I²C master device will switch the I²C bus to HS-mode by transmitting the above sequence
of bits on the I²C bus at a transfer rate of not more than 400 kbps. After that, the master can switch to HS-mode to
transfer data at a rate of up to 3.4 Mbps. The I²C bus switches back to F/S mode when the I²C master transmits a
STOP bit. Figure 30.4 shows this in clearer detail.
F/S-mode
S Master code N Sr SLA R/W A
HS-mode
DATA+ACKs
A/N P
F/S-mode
HS-mode
S Master code N Sr SLA R/W A DATA+ACKs A/N Sr SLA R/W A
P
Figure 30.4. Data Transfer Switching between F/S Mode and HS-Mode
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Rev 1.0