C8051F970-A-GM Datasheet, PDF (96/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
VDD ^{1.8 V to 3.6 V}
C8051F97x Device
GPIO
Analog
Peripherals
VREF
Temp Sensor
ADC0 CS0
AMUX0
VREG0
1.8 V
Sleep
PMU0
Digital
Peripherals
Active
Idle
Stop
Suspend
SmaRTClock
RAM
CIP-51 Core
Flash
Timers
UART
P0.0
P0.1
P0.2
P0.3
P6.1
Figure 16.2. C8051F97x Power Distribution
16.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All
analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle mode, the one-shot circuit should be enabled by
clearing the BYPASS bit (FLSCL.6).
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled
interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The
pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will
be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an
internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address
0x0000
If enabled, the watchdog timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the
Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent
write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering
the idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional
power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake
up the system. Refer to "27.6. PCA Watchdog Timer Reset" on page 326 for more information on the use and
configuration of the WDT.
96
Rev 1.0