C8051F970-A-GM Datasheet, PDF (196/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 21.7. DMA0NBAH: Memory Base Address High
Bit
7
6
5
4
3
2
1
0
Name
Reserved
NBAH
Type
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0xCA
Bit
Name
Function
7:4
Reserved Must write reset value.
3:0
NBAH Memory Base Address High.
This field sets high byte of the channel memory base address. This base address is the
starting channel XRAM address if the channel's address offset DMA0NAO is reset to 0.
Note: This register is a DMA channel indirect register. Select the desired channel first using the DMA0SEL register.
Rev 1.0
197