C8051F970-A-GM Datasheet, PDF (24/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
2.1. Power
2.1.1. Voltage Supply Monitor (VMON0)
The C8051F97x devices include a voltage supply monitor which allows devices to function in known, safe
operating condition without the need for external hardware.
The supply monitor module includes the following features:
Holds the device in reset if the main VDD supply drops below the VDD Reset threshold.
2.1.2. Device Power Modes
The C8051F97x devices feature seven low power modes in addition to normal operating mode, allowing the
designer to save power when the core is not in use. All power modes are detailed in Table 2.1.
Table 2.1. Power Modes
Power Mode
Description
Wake-up
Sources
Power and Performance
Normal Active
Device fully functional.
N/A
Excellent MIPS/mW
Low Power
Active
Device fully functional except
peripherals whose clocks are
intentionally disabled.
N/A
Excellent.
Clocks only enabled for peripher-
als that request for it.
Idle
All peripherals fully functional. Any Interrupt
Good
Wake-up in 2 clock cycles.
No Code Execution
Low Power Idle
Similar to Idle mode, the CPU is
halted. Clocks of unused peripher-
als can be intentionally gated.
Wake-up in 2 clock cycles.
Any Interrupt
Very Good
No Code Execution.
Clocks only enabled for peripher-
als that request for it.
Stop
Legacy 8051 low power mode.
A reset is required to wake up.
Any Reset
Good
No Code Execution
Precision Oscillator Disabled
Suspend
Similar to Stop mode, but very fast
wake-up time and code resumes
execution at the next instruction.
CS0,
SmaRTClock,
Port Match,
I²C Slave,
RST pin
Very Good
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Sleep
Ultra Low Power and flexible
wake-up sources. Code resumes
execution at the next instruction.
SmaRTClock,
Port Match,
I²C Slave,
RST pin
Excellent
Power Supply Gated
All Oscillators except
SmaRTClock Disabled
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