C8051F970-A-GM Datasheet, PDF (241/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
24. Clocking Sources
The C8051F97x devices can be clocked from the internal low-power 24.5 MHz oscillator, the internal low-power
20 MHz oscillator, the SmaRTClock real time clock oscillator, or externally by an external oscillator (not supported
on devices in the QFN-24 package). An adjustable clock divider allows the selected clock source to be post-scaled
by powers of 2, up to a factor of 128. By default, the system clock comes up as the 24.5 MHz oscillator divided by
8.
Option 2
VDD
Option 3
XTAL2
XTAL2
Option 1
XTAL1
10M
XTAL2
Option 4
XTAL2
OSCICL
OSCICN
CLKSEL
EN
Precision
Internal Oscillator
External
Oscillator
Drive Circuit
Precision Internal Oscillator
External Oscillator
Low Power Internal Oscillator
Low Power Internal
Oscillator Divided by 8
8
SmaRTClock Oscillator
CLKRDY
n
Clock Divider
SYSCLK
Low Power
Internal Oscillator
SmaRTClock
Oscillator
OSCXCN
Figure 24.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are being
changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
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