C8051F970-A-GM Datasheet, PDF (434/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 33.2. PCA0MD: PCA Mode
Bit
7
6
5
4
3
2
1
0
Name
CIDL
WDTE WDLCK Reserved
CPS
ECF
Type
RW
RW
RW
R
RW
RW
Reset
0
1
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xD9
Table 33.5. PCA0MD Register Bit Descriptions
Bit
Name
Function
7
CIDL PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6
WDTE Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Disable Watchdog Timer.
1: Enable PCA Module 2 as the Watchdog Timer.
5
WDLCK Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4
Reserved Must write reset value.
3:1
CPS PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter.
000: System clock divided by 12.
001: System clock divided by 4.
010: Timer 0 overflow.
011: High-to-low transitions on ECI (max rate = system clock divided by 4).
100: System clock.
101: External clock divided by 8 (synchronized with the system clock).
110: RTC divided by 8.
111: Reserved.
0
ECF PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Rev 1.0
435