C8051F970-A-GM Datasheet, PDF (352/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
29.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a
receiver during the address byte, and a receiver during all data bytes. When slave events are enabled (INH = 0),
the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in
this case) is received. If hardware ACK generation is disabled, upon entering Slave Receiver Mode, an interrupt is
generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or
ignore the received slave address with a NACK. If hardware ACK generation is enabled, the hardware will apply
the ACK for a slave address which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will
occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the next
START is detected. If the received slave address is acknowledged, zero or more data bytes are received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each received
byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and
then post the interrupt. It is important to note that the appropriate ACK or NACK value should be set up by
the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. The interface will switch to Slave Transmitter
Mode if SMB0DAT is written while an active Slave Receiver. Figure 29.7 shows a typical slave write sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK generation
is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after the ACK when
hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
WA
Data Byte
A
Data Byte
AP
Interrupts with Hardware ACK Disabled (EHACK = 0)
Received by SMBus
Interface
Transmitted by
SMBus Interface
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Figure 29.7. Typical Slave Write Sequence
Rev 1.0
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