C8051F970-A-GM Datasheet, PDF (294/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.10. P1MASK: Port 1 Mask
Bit
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0x8C
Table 26.13. P1MASK Register Bit Descriptions
Bit
Name
Function
7
B7
Port 1 Bit 7 Mask Value.
0: P1.7 pin logic value is ignored and will not cause a port mismatch event.
1: P1.7 pin logic value is compared to P1MAT.7.
6
B6
Port 1 Bit 6 Mask Value.
0: P1.6 pin logic value is ignored and will not cause a port mismatch event.
1: P1.6 pin logic value is compared to P1MAT.6.
5
B5
Port 1 Bit 5 Mask Value.
0: P1.5 pin logic value is ignored and will not cause a port mismatch event.
1: P1.5 pin logic value is compared to P1MAT.5.
4
B4
Port 1 Bit 4 Mask Value.
0: P1.4 pin logic value is ignored and will not cause a port mismatch event.
1: P1.4 pin logic value is compared to P1MAT.4.
3
B3
Port 1 Bit 3 Mask Value.
0: P1.3 pin logic value is ignored and will not cause a port mismatch event.
1: P1.3 pin logic value is compared to P1MAT.3.
2
B2
Port 1 Bit 2 Mask Value.
0: P1.2 pin logic value is ignored and will not cause a port mismatch event.
1: P1.2 pin logic value is compared to P1MAT.2.
1
B1
Port 1 Bit 1 Mask Value.
0: P1.1 pin logic value is ignored and will not cause a port mismatch event.
1: P1.1 pin logic value is compared to P1MAT.1.
0
B0
Port 1 Bit 0 Mask Value.
0: P1.0 pin logic value is ignored and will not cause a port mismatch event.
1: P1.0 pin logic value is compared to P1MAT.0.
Rev 1.0
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