C8051F970-A-GM Datasheet, PDF (337/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 28.1. SPI Slave Timing Parameters
Parameter Description
Min
Max
Units
Master Mode Timing (See Figure 28.8 and Figure 28.9)
T_MCKH
SCK High Time
T_MCKL
SCK Low Time
T_MIS
MISO Valid to SCK Shift Edge
T_MIH
SCK Shift Edge to MISO Change
Slave Mode Timing (See Figure 28.10 and Figure 28.11)
1 x T_SYSCLK
—
ns
1 x T_SYSCLK
—
ns
1 x T_SYSCLK + 20
—
ns
0
—
ns
T_SE
NSS Falling to First SCK Edge
T_SD
Last SCK Edge to NSS Rising
T_SEZ
NSS Falling to MISO Valid
T_SDZ
NSS Rising to MISO High-Z
T_CKH
SCK High Time
T_CKL
SCK Low Time
T_SIS
MOSI Valid to SCK Sample Edge
T_SIH
SCK Sample Edge to MOSI Change
T_SOH
SCK Shift Edge to MISO Change
T_SLH
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
2 x T_SYSCLK
2 x T_SYSCLK
—
—
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
—
6 x T_SYSCLK
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
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