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C8051F970-A-GM Datasheet, PDF (204/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash
C8051F97x
When the FRACMD bit is set to 1, the inputs are treated at 16-bit fractional values. The decimal point is located
between bits 15 and 14 of the data word. After the operation, the accumulator will contain a 40-bit fractional value,
with the decimal point located between bits 31 and 30. Figure 22.3 shows how fractional numbers are stored in the
SFRs.
MAC0AandMAC0BBitWeighting
HighByte
LowByte
s*1 2Ͳ1 2Ͳ2 2Ͳ3 2Ͳ4 2Ͳ5 2Ͳ6 2Ͳ7 2Ͳ8 2Ͳ9 2Ͳ10 2Ͳ11 2Ͳ12 2Ͳ13 2Ͳ14 2Ͳ15
If(MAC0SN==1),s=Ͳ1,otherwises=1
MAC0AccumulatorBitWeighting(norounding)
MAC0OVR
s*28 27 

MAC0ACC3:MAC0ACC2:MAC0ACC1:MAC0ACC0
21 20 2Ͳ1 2Ͳ2 2Ͳ3 

2Ͳ27 2Ͳ28 2Ͳ29 2Ͳ30 2Ͳ31
s=signofresult(1orͲ1)
MAC0Accumulatorroundedresult(MAC0RND=1)BitWeighting
MAC0ACC1
MAC0ACC0
s*1 2Ͳ1 2Ͳ2 2Ͳ3 2Ͳ4 2Ͳ5 2Ͳ6 2Ͳ7 2Ͳ8 2Ͳ9 2Ͳ10 2Ͳ11 2Ͳ12 2Ͳ13 2Ͳ14 2Ͳ15
s=signofresult(1orͲ1)
Figure 22.3. Fractional Mode Data Representation
22.3. Operating in Multiply and Accumulate Mode
MAC0 operates in multiply and accumulate (MAC) mode when the ACCMD bit (MAC0CF0.3) is cleared to 0. When
operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A and MAC0B
registers and adds the result to the contents of the 41-bit accumulator. A MAC operation takes 1 SYSCLK cycle to
complete. A rounded (and optionally, saturated) result is available when the MAC0RND bit is set.
If the CLRACC bit (MAC0CF0.5) is set to 1, the accumulator and all MAC0STA flags will be cleared during the next
SYSCLK cycle. The CLRACC bit will clear itself to 0 when the clear operation has completed.
22.4. Operating in Multiply Only Mode
MAC0 operates in multiply only mode when the ACCMD bit (MAC0CF0.5) is set to 1. Multiply only mode is
identical to Multiply and Accumulate mode, except that the multiplication result is added with a value of zero before
being stored in the 41-bit accumulator (i.e. it overwrites the current accumulator contents). As in MAC mode, the
rounded result can be read if the ROUND bit is set. Note that in Multiply Only mode, the HOVF flag is not affected.
Rev 1.0
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