C8051F970-A-GM Datasheet, PDF (372/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
I2C0 module – DMA mode – clock stretch – Write
1
Sleep
Active
2
S SLA W A
3
DB0 A
DB1 A
xa
b
c
1 SLA+W wakes CPU from sleep mode.
DB2 A Sr SLA W A
d
e
x
f
4 5 S = START
DB3 A
P ^{P = STOP}
A = ACK
N = NACK
R = Read
W = Write
g
h _{Sr = repeated START}
Shaded blocks are generated by
Slave device
2
INT generated. CPU configures DMA for I2C Write. SCL is held low until CPU clears I2C0INT.
3 DMA fetches DB0 from I2C0DIN and asserts i2c_dma_ack which releases SCL
4 DMA generates “done” interrupt. SCL is released by assertion of i2c_dma_ack. CPU disables DMA for I2C Write.
5 STOP generates interrupt. No Clock Stretch. CPU clears I2C0INT
No int x
I2C0 int a
No int b
No int c
No int d
I2C0 int e
I2C0STAT = x1001000 at 8^th SCL rising edge
I2C0STAT = x1101010; CPU clears START; CPU configures DMA for 4 bytes of I2C Write transfer and clears I2C0INT
I2C0STAT = x1000000; DMA transfers DB0 from I2C0DIN to XRAM
I2C0STAT = x1000000; DMA transfers DB1 from I2C0DIN to XRAM
I2C0STAT = x1000000; DMA transfers DB2 from I2C0DIN to XRAM
I2C0STAT = x0100000; CPU services end of transaction and clears I2C0INT
I2C0 int f
DMA int g
I2C0 int h
I2C0STAT = x1101010; CPU clears START; CPU configures DMA for I2C Write and clears I2C0INT
I2C0STAT = x1000000; DMA transfers DB3 from I2C0DIN to XRAM. CPU services DMA done interrupt
I2C0STAT = x0100100; CPU clears STOP and I2C0INT.
* At a, f: Bits are set at 9^th SCL falling edge. CPU clears I2C0INT to release SCL
* At b, c, d, f, g: i2c_dma_req asserted on 9^th SCL falling edge. I2c_dma_ack releases SCL
Figure 30.7. Typical I²C Write Sequence in DMA Mode
Rev 1.0
373