C8051F970-A-GM Datasheet, PDF (342/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
29. System Management Bus / I²C (SMBus0)
The SMBus I/O interface is a two-wire, bidirectional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I²C serial bus.
Reads and writes to the SMBus by the system controller are byte oriented with the SMBus interface autonomously
controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method
of extending the clock-low duration is available to accommodate devices with different speed capabilities on the
same bus.
The SMBus may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and
START/STOP control and generation. The SMBus peripherals can be fully driven by software (i.e., software
accepts/rejects slave addresses, and generates ACKs), or hardware slave address recognition and automatic ACK
generation can be enabled to minimize software overhead. A block diagram of the SMBus0 peripheral is shown in
Figure 29.1.
Data /
Address
SMB0DAT
SMBus0
Shift Register
SI
State Control
Logic
Slave Address
Recognition
Timers 0,
1 or 2
Master SCL Clock
Generation
Timer 3
SCL Low
SDA
SCL
Figure 29.1. SMBus0 Block Diagram
Rev 1.0
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