C8051F970-A-GM Datasheet, PDF (359/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 29.2. SMB0CN: SMBus 0 Control
Bit
7
6
5
4
3
2
1
0
Name MASTER TXMODE
STA
STO
ACKRQ ARBLOST ACK
SI
Type
R
R
RW
RW
R
R
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xC0 (bit-addressable)
Table 29.8. SMB0CN Register Bit Descriptions
Bit
Name
Function
7
MASTER SMBus Master/Slave Indicator.
This read-only bit indicates when the SMBus is operating as a master.
0: SMBus operating in slave mode.
1: SMBus operating in master mode.
6
TXMODE SMBus Transmit Mode Indicator.
This read-only bit indicates when the SMBus is operating as a transmitter.
0: SMBus in Receiver Mode.
1: SMBus in Transmitter Mode.
5
STA
SMBus Start Flag.
When reading STA, a '1' indicates that a start or repeated start condition was detected on
the bus.
Writing a '1' to the STA bit initiates a start or repeated start on the bus.
4
STO SMBus Stop Flag.
When reading STO, a '1' indicates that a stop condition was detected on the bus (in slave
mode) or is pending (in master mode).
When acting as a master, writing a '1' to the STO bit initiates a stop condition on the bus.
This bit is cleared by hardware.
3
ACKRQ SMBus Acknowledge Request.
0: No ACK requested.
1: ACK requested.
2
ARBLOST SMBus Arbitration Lost Indicator.
0: No arbitration error.
1: Arbitration error occurred.
1
ACK SMBus Acknowledge.
When read as a master, the ACK bit indicates whether an ACK (1) or NACK (0) is
received during the most recent byte transfer.
As a slave, this bit should be written to send an ACK (1) or NACK (0) to a master
request. Note that the logic level of the ACK bit on the SMBus interface is inverted from
the logic of the register ACK bit.
360
Rev 1.0