C8051F970-A-GM Datasheet, PDF (57/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
9. Special Function Register Memory Map
This section details the special function register memory map for the C8051F97x devices.
Table 9.1. C8051F97x SFR Memory Map
Address
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
F8
SPI0CN
I2C0STAT
PCA0L
—
PCA0H PCA0CPL0 PCA0CPH0 CS0THL
—
—
—
—
CS0THH VDM0CN 0
—
P5MDOUT F
F0
B
—
P4MDIN
—
P5MDIN
SFRNEXT
SMB0ADR
P0MAT
SMB0ADM
P1MAT
PCLKEN
EIP1
CLKMODE 0
EIP2
F
E8
ADC0CN
DMA0INT
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
—
—
—
P0MDIN
CS0DL
P1MDIN
CS0DH
P2MDIN
RSTSRC 0
P3MDIN F
E0 ACC
P3
DEVICEID
P4
REVID
P5
—
P6
—
FLWR
EIE1
EIE2
0
F
D8
PCA0CN
DMA0NCF
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 CS0SS
P0MDOUT
—
—
P1MDOUT P3MDOUT
CS0SE
IT01CF
PCA0PWM 0
P3MDOUT F
D0 PSW
REF0CN ADC0L
ADC0H ADC0MX
—
—
—
0
—
MAC0ACC0 MAC0ACC1 MAC0ACC2 MAC0ACC3 MAC0OVF MAC0ITER F
REG0CN TMR2RLL TMR2RLH TMR2L
TMR2H PMU0FL PMU0MD 0
C8 TMR2CN _{DMA0NBAL DMA0NBAH DMA0NAOL DMA0NAOH DMA0NSZL DMA0NSZH MAC0STA F}
C0
SMB0CN
MAC0CF0
SMB0CF
MAC0INTE
SMB0DAT
—
ADC0GTL ADC0GTH
P4MDOUT MAC0CF1
ADC0LTL
MAC0CF2
ADC0LTH
P1SKIP
—
P2SKIP
0
F
B8
IP
EMI0CN
P4DRV
ADC0AC
—
ADC0PWR
ADC0TK
CS0MD1
—
CS0MD2
—
CS0MD3 0
—
F
B0
CS0CN
—
OSCXCN
—
OSCICN
—
SFRLAST
—
PMU0CF
—
FLSCL
P0SKIP
FLKEY
0
F
A8
IE
CLKSEL
CS0CF
MAC0AL
CS0MX RTC0ADR RTC0DAT
MAC0AH I2C0CN I2C0SLAD MAC0BL
OSCICL 0
MAC0BH F
A0
P2
SPI0CFG
—
SPI0CKR
—
SPI0DAT
—
AMUX0P3
I2C0DOUT
AMUX0P4
I2C0DIN
AMUX0P5
SFRPGCN
SFRPAGE
0
F
98 SCON0
SBUF0
P0DRV
AMUX0P0 AMUX0P1 AMUX0P2 CRC0CNT CRC0AUTO CRC0FLIP 0
P1DRV
P2DRV
P3DRV
P5DRV
—
—
F
90
P1
TMR3CN TMR3RLL TMR3RLH TMR3L
DMA0BUSY DMA0EN
—
DMA0SEL
TMR3H
XBR0
CS0PM
XBR1
ADC0CF 0
P6MDIN F
88
TCON
DMA0MINT
TMOD
—
TL0
—
TL1
P0MASK
TH0
P1MASK
TH1
TOFFL
CKCON
TOFFH
PSCTL
0
F
80
P0
SP
DPL
DPH
CRC0CN
P2MASK
CRC0IN
P2MAT
CRC0DAT
—
PCON
0
F
denotes bit-addressable SFRs, bold indicates SFRs on all pages
Rev 1.0
57