C8051F970-A-GM Datasheet, PDF (286/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.2. XBR1: Port I/O Crossbar 1
Bit
7
6
5
4
3
2
1
0
Name WEAKPUD XBARE
Reserved
T1E
T0E
Type
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0x96
Table 26.5. XBR1 Register Bit Descriptions
Bit
Name
Function
7
WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode).
1: Weak Pullups disabled.
6
XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5:2
Reserved Must write reset value.
1
T1E
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
0
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
Rev 1.0
287