C8051F970-A-GM Datasheet, PDF (320/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.36. P6: Port 6 Pin Latch
Bit
7
6
5
4
3
2
1
0
Name
Reserved
B1
B0
Type
RW
RW
RW
Reset
0
0
0
0
0
0
1
1
SFR Page = 0x0; SFR Address: 0xE4
Table 26.39. P6 Register Bit Descriptions
Bit
Name
Function
7:2
Reserved Must write reset value.
1
B1
Port 6 Bit 1 Latch.
0: P6.1 is low. Set P6.1 to drive low.
1: P6.1 is high. Set P6.1 to drive or float high.
0
B0
Port 6 Bit 0 Latch.
0: P6.0 is low. Set P6.0 to drive low.
1: P6.0 is high. Set P6.0 to drive or float high.
Notes:
1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O.
2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input.
Register 26.37. P6MDIN: Port 6 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Reserved
B1
B0
Type
RW
RW
RW
Reset
0
0
0
0
0
0
1
1
SFR Page = 0xF; SFR Address: 0x97
Table 26.40. P6MDIN Register Bit Descriptions
Bit
Name
Function
7:2
Reserved Must write reset value.
1
B1
Port 6 Bit 1 Input Mode.
0: P6.1 pin is configured for analog mode.
1: P6.1 pin is configured for digital mode.
Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled.
Rev 1.0
321