C8051F970-A-GM Datasheet, PDF (325/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
27.3. Enabling the VDD Monitor
The VDD supply monitor is enabled by default. However, in systems which disable the supply monitor, it must be
enabled before selecting it as a reset source. Selecting the VDD supply monitor as a reset source before it has
stabilized may generate a system reset. In systems where this reset would be undesirable, a delay should be
introduced between enabling the VDD supply monitor and selecting it as a reset source. No delay should be
introduced in systems where software contains routines that erase or write flash memory. The procedure for
enabling the VDD supply monitor and selecting it as a reset source is:
1. Enable the VDD supply monitor (VMONEN = 1).
2. Wait for the VDD supply monitor to stabilize (optional).
3. Enable the VDD monitor as a reset source in the RSTSRC register.
27.4. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an
active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be
necessary to avoid erroneous noise-induced resets. The PINRSF flag is set on exit from an external reset.
27.5. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock
remains high or low for more than the MCD time window, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0.
Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin
is unaffected by this reset.
27.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to
prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled
or disabled by software as described in the PCA watchdog timer section. If a system malfunction prevents user
software from updating the WDT, a reset is generated and the WDTRSF bit is set to ‘1’. The state of the RST pin is
unaffected by this reset.
27.7. Flash Error Reset
If a flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur
due to any of the following:
A flash write or erase is attempted above user code space.
A flash read is attempted above user code space.
A program read is attempted above user code space (i.e. a branch instruction to the reserved area).
A flash read, write or erase attempt is restricted due to a flash security setting.
The FERROR bit is set following a flash error reset. The state of the RST pin is unaffected by this reset.
27.8. SmaRTClock Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRTClock Alarm.
The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector is enabled and the
SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs when the SmaRTClock
Alarm is enabled and the SmaRTClock timer value matches the ALARMn registers. The SmaRTClock can be
configured as a reset source by writing a 1 to the RTC0RE flag (RSTSRC.7). The SmaRTClock reset remains
functional even when the device is in the low power Suspend or Sleep mode. The state of the RST pin is
unaffected by this reset.
27.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit. The SWRSF bit will read 1 following a software forced
reset. The state of the RST pin is unaffected by this reset.
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