C8051F970-A-GM Datasheet, PDF (333/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
The SPI0 Clock Rate Register (SPI0CKR) controls the master mode serial clock frequency. This register is ignored
when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec)
is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave,
the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that
the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the slave’s
system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer
rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants
to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI
slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is
provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 28.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (4-Wire Mode)
Figure 28.6. Slave Mode Data/Clock Timing (CKPHA = 0)
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