C8051F970-A-GM Datasheet, PDF (117/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 17.4. ADC0PWR: ADC0 Power Control
Bit
7
6
5
4
3
2
1
0
Name ADLPM
Reserved
ADPWR
Type
RW
RW
RW
Reset
0
0
0
0
1
1
1
1
SFR Page = ALL; SFR Address: 0xBB
Table 17.5. ADC0PWR Register Bit Descriptions
Bit
Name
Function
7
ADLPM Low Power Mode Enable.
This bit can be used to reduce power to the ADC's internal common mode buffer. It can
be set to 1 to reduce power when tracking times in the application are longer (slower
sample rates).
0: Disable low power mode.
1: Enable low power mode (requires extended tracking time).
6:4
Reserved Must write reset value.
3:0
ADPWR Burst Mode Power Up Time.
This field sets the time delay allowed for the ADC to power up from a low power state.
When ADTM is set, an additional 3 SARCLKs are added to this time.
T_PWRTIME
=
8-----_{-----A----D----P----W-----R---}
F_HFOSC
Rev 1.0
117