C8051F970-A-GM Datasheet, PDF (86/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 13.4. EIE1 Register Bit Descriptions
Bit
Name
Function
0
ESMB0 SMBus (SMB0) Interrupt Enable.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
86
Rev 1.0