C8051F970-A-GM Datasheet, PDF (55/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
8.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F97x family implements 32 kB, or 16 kB of this
program memory space as in-system, re-programmable flash memory. The last address in the flash block (0x7FFF
on 32 kB devices and 0x3FFF on 16 kB devices) serves as a security lock byte for the device, and provides read,
write and erase protection. Addresses above the lock byte within the 64 kB address space are reserved.
C 8 0 5 1 F 9 7 0 /1 /2
Lock Byte
Lock Byte Page
0x7FFF
0x7FFE
0x7E00
Flash M em ory Space
C 8 0 5 1 F 9 7 3/4 /5
Lock Byte
Lock Byte Page
0x3FFF
0x3FFE
0x3E00
Flash M em ory Space
0x0000
Figure 8.2. Flash Program Memory Map
0x0000
8.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the C8051F97x
devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can be re-configured to write
and erase on-chip flash memory space. MOVC instructions are always used to read flash memory, while MOVX
write instructions are used to erase and write flash. This flash access feature provides a mechanism for the
C8051F97x to update program code and use the program memory space for non-volatile data storage. Refer to
Section “10. Flash Memory” on page 65 for further details.
8.2. Data Memory
The C8051F97x device family includes up to 512 bytes of RAM data memory. 256 bytes of this memory is mapped
into the internal RAM space of the 8051. On devices with 512 bytes total RAM, 256 additional bytes of memory are
available as on-chip “external” memory. The data memory map is shown in Figure 8.1 for reference.
8.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower
128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect
addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are
addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The
next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible
with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same
address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The
addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU
accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will
access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data
memory. Figure 8.1 illustrates the data memory organization of the C8051F97x.
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