C8051F970-A-GM Datasheet, PDF (347/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 29.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using software acknowledgment, the s/
w delay occurs between the time SMB0DAT or ACK is written and when SI0 is cleared. Note that if SI is cleared in the
same write that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts
(see Section “29.3.4. SCL Low Timeout” on page 345). The SMBus interface will force the associated timer to
reload while SCL is high, and allow the timer to count when SCL is low. The timer interrupt service routine should
be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be
considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 29.4).
29.4.2. SMBus Pin Swap
The SMBus peripheral is assigned to pins using the priority crossbar decoder. By default, the SMBus signals are
assigned to port pins starting with SDA on the lower-numbered pin, and SCL on the next available pin. The SWAP
bit in the SMBTC register can be set to 1 to reverse the order in which the SMBus signals are assigned.
29.4.3. SMBus Timing Control
The SDD field in the SMBTC register is used to restrict the detection of a START condition under certain
circumstances. In some systems where there is significant mis-match between the impedance or the capacitance
on the SDA and SCL lines, it may be possible for SCL to fall after SDA during an address or data transfer. Such an
event can cause a false START detection on the bus. These kind of events are not expected in a standard SMBus
or I2C-compliant system. In most systems this parameter should not be adjusted, and it is recommended
that it be left at its default value.
By default, if the SCL falling edge is detected after the falling edge of SDA (i.e. one SYSCLK cycle or more), the
device will detect this as a START condition. The SDD field is used to increase the amount of hold time that is
required between SDA and SCL falling before a START is recognized. An additional 2, 4, or 8 SYSCLKs can be
added to prevent false START detection in systems where the bus conditions warrant this.
29.4.4. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information. The higher four bits of SMB0CN
(MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER
indicates whether a device is the master or slave during the current transfer. TXMODE indicates whether the
device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt.
STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a 1 to
STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free
(STA is not cleared by hardware after the START is generated). Writing a 1 to STO while in Master Mode will cause
the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both
set (while in Master Mode), a STOP followed by a START will be generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is
transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition.
ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when
an arbitration is lost; see Table 29.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus
is stalled until software clears SI.
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