C8051F970-A-GM Datasheet, PDF (348/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
29.4.4.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incoming slave
addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing the ACK bit defines
the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received during the last ACK
cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ
is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated
if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately
following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not
acknowledged, further slave events will be ignored until the next START is detected.
29.4.4.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK generation is
enabled. More detail about automatic slave address recognition can be found in Section 29.4.5. As a receiver, the
value currently specified by the ACK bit will be automatically sent on the bus during the ACK cycle of an incoming
data byte. As a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. The ACKRQ bit
is not used when hardware ACK generation is enabled. If a received slave address is NACKed by hardware,
further slave events will be ignored until the next START is detected, and no interrupt will be generated.
Table 29.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 29.5 for SMBus status
decoding using the SMB0CN register.
Table 29.3. Sources for Hardware Changes to SMB0CN
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
Set by Hardware When:
A START is generated.
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low 
(ACKNOWLEDGE).
Cleared by Hardware When:
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
Must be cleared by software.
A pending STOP is generated.
After each ACK cycle.
Each time SIn is cleared.
The incoming ACK value is high
(NOT ACKNOWLEDGE).
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