C8051F970-A-GM Datasheet, PDF (284/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
WEAKPUD
(Weak Pull-Up Disable)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
VDD
VDD
(WEAK)
PORT
PAD
PxMDIN.x
(1 for digital)
(0 for analog)
To/From Analog
Peripheral
GND
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 26.4. Port I/O Cell Block Diagram
26.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on one or more port I/O pins.
A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of the
associated port pins (for example, P0MATCH.0 would correspond to P0.0). A port mismatch event occurs if the
logic levels of the port’s input pins no longer match the software controlled value. This allows software to be notified
if a certain change or pattern occurs on the input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which pins should be compared against the PnMATCH
registers. A port mismatch event is generated if (Pn & PnMASK) does not equal (PnMATCH & PnMASK) for all
ports with a PnMAT and PnMASK register.
A port mismatch event may be used to generate an interrupt or wake the device from idle mode. See the interrupts
and power options chapters for more details on interrupt and wake-up sources.
26.6. Direct Read/Write Access to Port I/O Pins
All port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable
and bit addressable. When writing to a port, the value written to the SFR is latched to maintain the output data
value at each pin. When reading, the logic levels of the port's input pins are returned regardless of the XBRn
settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its
corresponding port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a
Port Latch register as the destination. The read-modify-write instructions when operating on a port SFR are the
following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an
individual bit in a port SFR. For these instructions, the value of the latch register (not the pin) is read, modified, and
written back to the SFR.
Rev 1.0
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