C8051F970-A-GM Datasheet, PDF (282/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Registers XBR0 and XBR1are used to assign the digital I/O resources to the physical I/O port pins. Note that when
the SMBus is selected, the crossbar assigns both pins associated with the SMBus (SDA and SCL); when UART0 is
selected, the crossbar assigns both pins associated with UART0 (TX and RX). Standard port I/Os appear
contiguously after the prioritized functions have been assigned.
Figure 26.3 shows an example of the resulting pin assignments of the device with SMBus0, SPI0, and two
channels of PCA0 enabled and P0.3, P0.4, P1.0, and P1.1 skipped (P0SKIP = 0x18, P1SKIP = 0x03). SMBus0 is
the highest priority and it will be assigned first. The next-highest enabled peripheral is SPI0. P0.2 is available, so
SPI0 takes this pin. The next pins, MISO, MOSI, and NSS are routed to P0.5, P0.6, and P0.7, respectively,
because P0.3 and P0.4 are skipped. The PCA0 CEX0 and CEX1are then routed to P1.2 and P1.3. The other pins
on the device are available for use as general-purpose digital I/O or analog functions.
Port
P0
P1
P2
P3 P4 P5 P6
PinNumber 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 X X X X
QFN-24 Package
QFN-32 Package
QFN-48 Package
SMB0-SDA
SMB0-SCL
UART0-TX
UART0-RX
SPI0-SCK
SPI0-MISO
SPI0-MOSI
SPI0-NSS*
SYSCLK
PCA0-CEX0
PCA0-CEX1
PCA0-CEX2
PCA0-ECI
Timer0-T0
Timer1-T1
000110001100000000000000
Pin Skip Settings
P0SKIP
P1SKIP
P2SKIP
The crossbar peripherals are assigned in priority order from top to bottom.
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are enabled, the Crossbar should be manually configured to skip the
corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to 1.
* NSS is only pinned out when the SPI is in 4-wire mode.
Figure 26.3. Crossbar Priority Decoder Example
Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits
in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a port pin.
Rev 1.0
283