C8051F970-A-GM Datasheet, PDF (143/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
18.15. Capacitive Sense Register
Register 18.1. CS0CN: Capacitive Sense 0 Control
Bit
7
6
5
4
3
2
Name CSEN
CSEOS
CSINT CSBUSY CSCMPEN Reserved
Type
RW
R
RW
RW
RW
R
Reset
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xB0 (bit-addressable)
1
CSPME
R
0
0
CSCMPF
R
0
Bit
Name
Function
7
CSEN CS0 Enable.
0: CS0 disabled and in low-power mode.
1: CS0 enabled and ready to convert.
6
CSEOS CS0 End of Scan Interrupt Flag.
This bit must be cleared by firmware.
0: CS0 has not completed a scan since the last time CS0EOS was cleared.
1: CS0 has completed a scan.
5
CSINT CS0 Interrupt Flag.
This bit must be cleared by firmware.
0: CS0 has not completed a data conversion since the last time CS0INT was cleared.
1: CS0 has completed a data conversion.
4
CSBUSY CS0 Busy.
Read: A 1 indicates a CS0 conversion is in progress.
Write: Writing a 1 to this bit initiates a CS0 conversion if CS0CM[2:0] = 000b, 110b, or
111b.
3
CSCMPEN CS0 Digital Comparator Enable.
Enables the digital comparator, which compares accumulated CS0 conversion output to
the value stored in CS0THH:CS0THL.
0: Disable CS0 digital comparator.
1: Enable CS0 digital comparator.
2
Reserved Must write reset value.
1
CSPME CS0 Pin Monitor Event.
Set if any converter re-tries have occurred due to a pin monitor event. This bit must be
cleared by firmware.
0
CSCMPF CS0 Digital Comparator Interrupt Flag.
0: CS0 result is smaller than the value set by CS0THH and CS0THL since the last time
CS0CMPF was cleared.
1: CS0 result is greater than the value set by CS0THH and CS0THL since the last time
CS0CMPF was cleared.
Rev 1.0
143