C8051F970-A-GM Datasheet, PDF (391/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and
operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as
described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4–
TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or ignored when
reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow
flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are enabled.
The CT0 bit in the TMOD register selects the counter/timer's clock source. When CT0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register. Clearing CT selects the clock defined
by the T0M bit in register CKCON. When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared,
Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON.
Setting the TR0 bit enables the timer when either GATE0 in the TMOD register is logic 0 or the input signal INT0 is
active as defined by bit IN0PL in register IT01CF. Setting GATE0 to 1 allows the timer to be controlled by the
external input signal INT0, facilitating pulse width measurements
TR0
GATE0
0
X
1
0
1
1
1
1
Note: X = Don't Care
INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value
before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1
is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal INT1 is
used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF.
T0M
CT0
Pre-scaled Clock
0
SYSCLK
0
1
1
T0
GATE0
TR0
TCLK
TL0
(5 bits)
TH0
(8 bits)
TF0
(Interrupt Flag)
INT0
IN0PL _XOR
Figure 32.1. T0 Mode 0 Block Diagram
32.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers
are enabled and configured in Mode 1 in the same manner as for Mode 0.
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