C8051F970-A-GM Datasheet, PDF (259/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
25.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in order to
achieve the lowest possible power consumption. Automatic Gain Control automatically detects when the oscillation
amplitude has reached a point where it safe to reduce the drive current, therefore, it may be enabled during crystal
startup. It is recommended to enable Automatic Gain Control in most systems which use the SmaRTClock
oscillator in Crystal Mode. The following are recommended crystal specifications and operating conditions when
Automatic Gain Control is enabled:
ESR < 50 k
Load Capacitance < 10 pF
Supply Voltage < 3.0 V
Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure that the
chosen crystal will oscillate under the worst case condition to which the system will be exposed. The worst case
condition that should result in the least robust oscillation is at the following system conditions: lowest temperature,
highest supply voltage, highest ESR, highest load capacitance, and lowest bias current (AGC enabled, Bias
Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as the
system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull digital
output. The positive duty cycle of the output clock can be used as an indicator of oscillation robustness. As shown
in Figure 25.2, duty cycles less than 55% indicate a robust oscillation. As the duty cycle approaches 60%,
oscillation becomes less reliable and the risk of clock failure increases. Increasing the bias current (by disabling
AGC) will always improve oscillation robustness and will reduce the output clock’s duty cycle. This test should be
performed at the worst case system conditions, as results at very low temperatures or high supply voltage will vary
from results taken at room temperature or low supply voltage.
Safe Operating Zone
Low Risk of Clock High Risk of Clock
Failure
Failure
25%
55%
60%
Duty Cycle
Figure 25.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at the cost
of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will provide the crystal
oscillator with higher immunity against external factors which may lead to clock failure. Automatic Gain Control
must be disabled if using the SmaRTClock oscillator in self-oscillate mode.
Table 25.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows the
self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in crystal
mode. High crystal drive strength is recommended when the crystal is exposed to poor environmental conditions
such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting BIASX2 (RTC0XCN.5) to 1.
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