C8051F970-A-GM Datasheet, PDF(324/454 Page) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

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C8051F970-A-GM Datasheet, PDF (324/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

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C8051F97x

27.2. Power-Fail Reset / Supply Monitor

C8051F97x devices have a supply monitor that is enabled and selected as a reset source after each power-on or

power fail reset.

When enabled and selected as a reset source, any power down transition or power irregularity that causes VDD to

drop below VRST will cause the RST pin to be driven low and the CIP-51 will be held in a reset state (see

Figure 27.3). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state.

After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD supply monitor is

enabled and selected as a reset source. The enable state of the VDD supply monitor and its selection as a reset

source is only altered by power-on and power-fail resets. For example, if the VDD supply monitor is deselected as a

reset source and disabled by software, then a software reset is performed, the VDD supply monitor will remain

disabled and deselected after the reset.

In battery-operated systems, the contents of RAM can be preserved near the end of the batteryâs usable life if the

device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep Mode, the power-

fail reset is automatically disabled and the contents of RAM are preserved as long as VDD does not fall below

VPOR. A large capacitor can be used to hold the power supply voltage above VPOR while the user is replacing the

battery. Upon waking from Sleep mode, the enable and reset source select state of the VDD supply monitor are

restored to the value last set by the user.

To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when the VDD

supply falls below the VWARN threshold. The VDDOK bit can be configured to generate an interrupt. See Section

â13. Interruptsâ on page 79 for more details.

Important Note: To protect the integrity of Flash contents, the VDD supply monitor must be enabled and

selected as a reset source if software contains routines which erase or write Flash memory. If the VDD

supply monitor is not enabled, any erase or write performed on Flash memory will cause a Flash Error device

reset. memory. If the VDD supply monitor is not enabled, any erase or write performed on flash memory will be

ignored.

VDD

Reset Threshold

(VRST)

t

RST

VDD Monitor

Reset

Figure 27.3. VDD Supply Monitor Threshold

Rev 1.0

325

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