C8051F970-A-GM Datasheet, PDF (390/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.1. Timer 0 and Timer 1
Timer 0 and Timer 1 are each implemented as a16-bit register accessed as two separate bytes: a low byte (TL0 or
TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register.
Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register. Both counter/timers operate in one of
four primary modes selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer Mode register
(TMOD). Each timer can be configured independently for the operating modes described below.
Rev 1.0
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