C8051F970-A-GM Datasheet, PDF (107/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
17.3. Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK) is a divided version
of the system clock when burst mode is disabled (BURSTEN = 0), or a divided version of the low power oscillator
when burst mode is enabled (BURSEN = 1). The clock divide value is determined by the AD0SC bits in the
ADC0CF register.
17.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the following:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed “on-demand”.
During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The
falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). When
polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is
available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. When Timer 2 or Timer 3
overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte
overflows are used if Timer 2/3 is in 16-bit mode. See “32. Timers (Timer0, Timer1, Timer2, and Timer3)” on
page 390 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To
configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See “26. Port I/O (Port 0, Port 1, Port 2, Port
3, Port 4, Port 5, Port 6, Crossbar, and Port Match)” on page 278 for details on Port I/O configuration.
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