C8051F970-A-GM Datasheet, PDF (173/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
While CIP-51 executes in-line code (reading a value from I2C0STAT in this example), the SPI0 interrupt occurs.
The CIP-51 vectors to the SPI0 ISR and pushes the current SFR page value (SFR page 0x0F) into SFRNEXT in
the SFR page stack. The SFR page needed to access SPI0's SFRs is then automatically placed in the SFRPAGE
register (SFR page 0x00). SFRPAGE is considered the top of the SFR page stack. Firmware can now access the
SPI0 SFRs. Software may switch to any SFR page by writing a new value to the SFRPAGE register at any time
during the SPI0 ISR to access SFRs that are not on SFR page 0x00. See Figure 20.4.
SFRPAGE
pushed to
SFRNEXT
SFR Page 0x00
Automatically
pushed on stack
in SFRPAGE on
SPI0 interrupt
0x00
(SPI0)
0x0F
(I2C0STAT)
SFR Page
Stack SFRs
SFRPAGE
SFRNEXT
SFRLAST
Figure 20.4. SFR Page Stack after SPI0 Interrupt Occurs
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Rev 1.0