C8051F970-A-GM Datasheet, PDF (339/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 28.2. SPI0CN: SPI0 Control
Bit
7
6
5
4
Name
SPIF
WCOL
MODF RXOVRN
Type
RW
RW
RW
RW
Reset
0
0
0
0
SFR Page = 0x0; SFR Address: 0xF8 (bit-addressable)
3
2
NSSMD
RW
0
1
1
TXBMT
R
1
0
SPIEN
RW
0
Table 28.3. SPI0CN Register Bit Descriptions
Bit
Name
Function
7
SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are
enabled, an interrupt will be generated. This bit is not automatically cleared by hardware,
and must be cleared by firmware.
6
WCOL Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When this
occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. If
SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically
cleared by hardware, and must be cleared by firmware.
5
MODF Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected (NSS is
low, MSTEN = 1, and NSSMD = 01). If SPI interrupts are enabled, an interrupt will be
generated. This bit is not automatically cleared by hardware, and must be cleared by
firmware.
4
RXOVRN Receive Overrun Flag.
This bit is valid for slave mode only and is set to logic 1 by hardware when the receive
buffer still holds unread data from a previous transfer and the last bit of the current trans-
fer is shifted into the SPI0 shift register. If SPI interrupts are enabled, an interrupt will be
generated. This bit is not automatically cleared by hardware, and must be cleared by
firmware.
3:2
NSSMD Slave Select Mode.
Selects between the following NSS operation modes:
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode. NSS is an input to the device.
10: 4-Wire Single-Master Mode. NSS is an output and logic low.
11: 4-Wire Single-Master Mode. NSS is an output and logic high.
1
TXBMT Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic
1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPIEN SPI0 Enable.
0: Disable the SPI module.
1: Enable the SPI module.
340
Rev 1.0