C8051F970-A-GM Datasheet, PDF (346/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
The SMBCS bit field selects the SMBus clock source, which is used only when operating as a master or when the
Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the
absolute minimum SCL low and high times as defined in Equation 29.1.The selected clock source may be shared
by other peripherals so long as the timer is left running at all times.
T_HighMin
=
T_LowMin
=
----------------------1-----------------------
f_{ClockSourceOverflow}
Equation 29.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 29.1. When the interface is operating as a master (and SCL is not driven or extended by any other
devices on the bus), the typical SMBus bit rate is approximated by Equation 29.2.
BitRate = -^f-^C----^l-^o---^c--^k--^S---^o--^u---^r--^c--^e--^O----^v--^e--^r--^f--^l-^o---^w-
3
Equation 29.2. Typical SMBus Bit Rate
Figure 29.4 shows the typical SCL generation described by Equation 29.2. Notice that T_HIGH is typically twice as
large as T_LOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by
slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will
never exceed the limits defined by equation Equation 29.1.
Timer Source
Overflows
SCL
T_Low
T_High
SCL High Timeout
Figure 29.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup
time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum
SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions
from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus
Specification requirements of 250 ns and 300 ns, respectively. Table 29.2 shows the minimum setup and hold
times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary for SMBus
compliance when SYSCLK is above 10 MHz.
EXTHOLD
0
1
Table 29.2. Minimum SDA Setup and Hold Times
Minimum SDA Setup Time
T_low – 4 system clocks
or
1 system clock + s/w delay^*
11 system clocks
Minimum SDA Hold Time
3 system clocks
12 system clocks
Rev 1.0
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