C8051F970-A-GM Datasheet, PDF (398/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.3.2. 8-Bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-
reload mode as shown in Figure 32.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload
value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when
configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock source
divided by 8, or the SmaRTClock. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either
SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN), as follows:
T3MH
0
0
0
0
1
T3XCLK[1:0] TMR3H Clock
Source
00
SYSCLK / 12
01
SmaRTClock
10
Reserved
11
External Clock / 8
X
SYSCLK
T3ML
0
0
0
0
1
T3XCLK[1:0] TMR3L Clock
Source
00
SYSCLK / 12
01
SmaRTClock
10
Reserved
11
External Clock / 8
X
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows from
0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer
3 interrupts are enabled and TF3LINT (TMR3CN.5) is set, an interrupt is generated each time either TMR3L or
TMR3H overflows. When TF3LINT is enabled, software must check the TF3H and TF3L flags to determine the
source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared by hardware and must be man-
ually cleared by software.
T3XCLK[1:0]
SYSCLK / 12
00
SmaRTClock
01
External Clock / 8
11
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
TMR3RLH ^Reload
0
TCLK
TR3
TMR3H
1
TMR3RLL ^Reload
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Interrupt
1
TCLK _TMR3L
To ADC
0
Figure 32.8. Timer 3 8-Bit Mode Block Diagram
Rev 1.0
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