C8051F970-A-GM Datasheet, PDF (364/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30. I²C Slave
The I2CSLAVE0 interface is a 2-wire, bidirectional serial bus that is compatible with the I²C Bus Specification 3.0. It
is capable of transferring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps. Either the CPU or the DMA
can write to the I²C interface, and the I²C interface can autonomously control the serial transfer of data. The
interface also supports clock stretching for cases where the CPU may be temporarily prohibited from transmitting a
byte or processing a received byte during an I²C transaction. It can also operate in sleep mode without an active
system clock and wake the CPU when a matching slave address is received.
It operates only as an I²C slave device. The I2CSLAVE0 peripheral provides control of the SCL (serial clock)
synchronization, SDA (serial data), SCL Clock stretching, I²C arbitration logic, and low power mode operation. The
block diagram of the I2CSLAVE0 peripheral and the associated SFRs is shown in Figure 30.1.
I2C0SLAD
I2C0STAT
I2C0CNTL
I2C0 Slave Control Logic
DMA interface ^{- SCL Synchronization}
- SDA Control
- Clock stretching
- DMA interface
- Hardware Slave Address Recognition
- Automatic ACK generation
I²C interrupt and _{- IRQ generation}
wake-up signalling _{- I2C Pad Selection}
- SCL Timeout detection (via Timer 3)
- High speed mode detection
- Wake-on-address-match operation during sleep
mode
- Low power mode operation
DMA transfer from XRAM
I2C0DIN
Buffer_In
I2C0DOUT
Buffer_Out
SCL
SDA
DMA transfer to XRAM
Figure 30.1. I2CSLAVE0 Block Diagram
Rev 1.0
365