C8051F970-A-GM Datasheet, PDF (29/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
2.5.4. High-Speed I2C Slave (I2CSLAVE0)
The I2C Slave 0 interface is a 2-wire, bidirectional serial bus that is compatible with the I²C Bus Specification 3.0. It
is capable of transferring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps. Either the CPU or the DMA
can write to the I²C interface, and the I²C interface can autonomously control the serial transfer of data. The
interface also supports clock stretching for cases where the CPU may be temporarily prohibited from transmitting a
byte or processing a received byte during an I²C transaction. It can also operate in sleep mode without an active
system clock and wake the CPU when a matching slave address is received.
It operates only as an I²C slave device. The I2CSLAVE0 peripheral provides control of the SCL (serial clock)
synchronization, SDA (serial data), SCL Clock stretching, I²C arbitration logic, and low power mode operation.
The I2C Slave 0 module includes the following features:
High-speed (up to 3.4 Mbps), fast (400 kbps), and standard (up to 100 kbps) transfer speeds.
Support for slave mode only.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Can operate in sleep mode without an active system clock and wake the CPU after receiving a matching
slave address.
Internal pull-up resistors.
2.5.5. 16/32-bit CRC (CRC0)
The CRC module is designed to provide hardware calculations for flash memory verification and communications
protocols. The CRC module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the
following features:
Support for four CCITT-16 polynomial.
Byte-level bit reversal.
Automatic CRC of flash contents on one or more 256-byte blocks.
Initial seed selection of 0x0000 or 0xFFFF.
2.6. Analog Peripherals
2.6.1. 10-Bit Analog-to-Digital Converter (ADC0)
The ADC0 module on C8051F97x devices is a Successive Approximation Register (SAR) Analog to Digital
Converter (ADC). The key features of the ADC module are:
Single-ended 10-bit mode.
Supports an output update rate of 300 ksps samples per second.
Selectable asynchronous hardware conversion trigger.
Output data window comparator allows automatic range checking.
Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with
programmable power-on settling and tracking time.
Conversion complete and window compare interrupts supported.
Flexible output data formatting.
Includes an internal 1.65 V fast-settling reference with two levels and support for an external reference.
Rev 1.0
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