C8051F970-A-GM Datasheet, PDF (287/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
26.8. Port I/O Control Registers
Register 26.3. P0MASK: Port 0 Mask
Bit
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0x8B
Table 26.6. P0MASK Register Bit Descriptions
Bit
Name
Function
7
B7
Port 0 Bit 7 Mask Value.
0: P0.7 pin logic value is ignored and will not cause a port mismatch event.
1: P0.7 pin logic value is compared to P0MAT.7.
6
B6
Port 0 Bit 6 Mask Value.
0: P0.6 pin logic value is ignored and will not cause a port mismatch event.
1: P0.6 pin logic value is compared to P0MAT.6.
5
B5
Port 0 Bit 5 Mask Value.
0: P0.5 pin logic value is ignored and will not cause a port mismatch event.
1: P0.5 pin logic value is compared to P0MAT.5.
4
B4
Port 0 Bit 4 Mask Value.
0: P0.4 pin logic value is ignored and will not cause a port mismatch event.
1: P0.4 pin logic value is compared to P0MAT.4.
3
B3
Port 0 Bit 3 Mask Value.
0: P0.3 pin logic value is ignored and will not cause a port mismatch event.
1: P0.3 pin logic value is compared to P0MAT.3.
2
B2
Port 0 Bit 2 Mask Value.
0: P0.2 pin logic value is ignored and will not cause a port mismatch event.
1: P0.2 pin logic value is compared to P0MAT.2.
1
B1
Port 0 Bit 1 Mask Value.
0: P0.1 pin logic value is ignored and will not cause a port mismatch event.
1: P0.1 pin logic value is compared to P0MAT.1.
0
B0
Port 0 Bit 0 Mask Value.
0: P0.0 pin logic value is ignored and will not cause a port mismatch event.
1: P0.0 pin logic value is compared to P0MAT.0.
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Rev 1.0