MMC2107 Datasheet, PDF (94/618 Pages) –

Freescale Semiconductor, Inc.
Chip Configuration Module (CCM)
3.7.2 Memory Map
Table 3-3. Chip Configuration Module Memory Map
Address
Bits 31–16
Bits 15–0
Access⁽¹⁾
0x00c1_0000
Chip configuration register (CCR)
Reserved⁽²⁾
S
0x00c1_0004 Reset configuration register (RCON)
Chip identification register (CIR)
S
0x00c1_0008
Chip test register (CTR)
Reserved⁽²⁾
S
0x00c1_000c
Unimplemented⁽³⁾
—
1. S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a
cycle termination transfer error.
2. Writing to reserved addresses has no effect; reading returns 0s.
3. Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
3.7.3 Register Descriptions
The following subsection describes the CCM registers.
3.7.3.1 Chip Configuration Register
Address: 0x00c1_0000 and 0x00c1_0001
Bit 15
14
13
12
11
10
9
Bit 8
Read:
0
0
MODE2 MODE1 MODE0
LOAD
SHEN EMINT
Write:
Reset: Note 1
0
Note 2 Note 2
0
Note 1 Note 1 Note 1
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
SZEN PSTEN SHINT BME
BMD BMT1 BMT0
Reset: 0
Note 3 Note 2
0
1
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Notes:
1. Determined during reset configuration
2. 0 for all configurations except emulation mode, 1 for emulation mode
3. 0 for all configurations except emulation and master modes, 1 for emulation and master
modes
Figure 3-2. Chip Configuration Register (CCR)
Technical Data
94
Chip Configuration Module (CCM)
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MMC2107 – Rev. 2.0
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